
other-stack:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400538 <_init>:
  400538:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40053c:	910003fd 	mov	x29, sp
  400540:	9400003a 	bl	400628 <call_weak_fn>
  400544:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400548:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400550 <.plt>:
  400550:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400554:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf3e0>
  400558:	f947fe11 	ldr	x17, [x16, #4088]
  40055c:	913fe210 	add	x16, x16, #0xff8
  400560:	d61f0220 	br	x17
  400564:	d503201f 	nop
  400568:	d503201f 	nop
  40056c:	d503201f 	nop

0000000000400570 <malloc@plt>:
  400570:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400574:	f9400211 	ldr	x17, [x16]
  400578:	91000210 	add	x16, x16, #0x0
  40057c:	d61f0220 	br	x17

0000000000400580 <__libc_start_main@plt>:
  400580:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400584:	f9400611 	ldr	x17, [x16, #8]
  400588:	91002210 	add	x16, x16, #0x8
  40058c:	d61f0220 	br	x17

0000000000400590 <__gmon_start__@plt>:
  400590:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400594:	f9400a11 	ldr	x17, [x16, #16]
  400598:	91004210 	add	x16, x16, #0x10
  40059c:	d61f0220 	br	x17

00000000004005a0 <abort@plt>:
  4005a0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005a4:	f9400e11 	ldr	x17, [x16, #24]
  4005a8:	91006210 	add	x16, x16, #0x18
  4005ac:	d61f0220 	br	x17

00000000004005b0 <puts@plt>:
  4005b0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005b4:	f9401211 	ldr	x17, [x16, #32]
  4005b8:	91008210 	add	x16, x16, #0x20
  4005bc:	d61f0220 	br	x17

00000000004005c0 <free@plt>:
  4005c0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005c4:	f9401611 	ldr	x17, [x16, #40]
  4005c8:	9100a210 	add	x16, x16, #0x28
  4005cc:	d61f0220 	br	x17

00000000004005d0 <printf@plt>:
  4005d0:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  4005d4:	f9401a11 	ldr	x17, [x16, #48]
  4005d8:	9100c210 	add	x16, x16, #0x30
  4005dc:	d61f0220 	br	x17

Disassembly of section .text:

00000000004005e0 <_start>:
  4005e0:	d280001d 	mov	x29, #0x0                   	// #0
  4005e4:	d280001e 	mov	x30, #0x0                   	// #0
  4005e8:	aa0003e5 	mov	x5, x0
  4005ec:	f94003e1 	ldr	x1, [sp]
  4005f0:	910023e2 	add	x2, sp, #0x8
  4005f4:	910003e6 	mov	x6, sp
  4005f8:	580000c0 	ldr	x0, 400610 <_start+0x30>
  4005fc:	580000e3 	ldr	x3, 400618 <_start+0x38>
  400600:	58000104 	ldr	x4, 400620 <_start+0x40>
  400604:	97ffffdf 	bl	400580 <__libc_start_main@plt>
  400608:	97ffffe6 	bl	4005a0 <abort@plt>
  40060c:	00000000 	.inst	0x00000000 ; undefined
  400610:	004009c8 	.word	0x004009c8
  400614:	00000000 	.word	0x00000000
  400618:	00400a50 	.word	0x00400a50
  40061c:	00000000 	.word	0x00000000
  400620:	00400ad0 	.word	0x00400ad0
  400624:	00000000 	.word	0x00000000

0000000000400628 <call_weak_fn>:
  400628:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf3e0>
  40062c:	f947f000 	ldr	x0, [x0, #4064]
  400630:	b4000040 	cbz	x0, 400638 <call_weak_fn+0x10>
  400634:	17ffffd7 	b	400590 <__gmon_start__@plt>
  400638:	d65f03c0 	ret
  40063c:	00000000 	.inst	0x00000000 ; undefined

0000000000400640 <deregister_tm_clones>:
  400640:	b0000080 	adrp	x0, 411000 <malloc@GLIBC_2.17>
  400644:	91012000 	add	x0, x0, #0x48
  400648:	b0000081 	adrp	x1, 411000 <malloc@GLIBC_2.17>
  40064c:	91012021 	add	x1, x1, #0x48
  400650:	eb00003f 	cmp	x1, x0
  400654:	540000a0 	b.eq	400668 <deregister_tm_clones+0x28>  // b.none
  400658:	90000001 	adrp	x1, 400000 <_init-0x538>
  40065c:	f9457821 	ldr	x1, [x1, #2800]
  400660:	b4000041 	cbz	x1, 400668 <deregister_tm_clones+0x28>
  400664:	d61f0020 	br	x1
  400668:	d65f03c0 	ret
  40066c:	d503201f 	nop

0000000000400670 <register_tm_clones>:
  400670:	b0000080 	adrp	x0, 411000 <malloc@GLIBC_2.17>
  400674:	91012000 	add	x0, x0, #0x48
  400678:	b0000081 	adrp	x1, 411000 <malloc@GLIBC_2.17>
  40067c:	91012021 	add	x1, x1, #0x48
  400680:	cb000021 	sub	x1, x1, x0
  400684:	9343fc21 	asr	x1, x1, #3
  400688:	8b41fc21 	add	x1, x1, x1, lsr #63
  40068c:	9341fc21 	asr	x1, x1, #1
  400690:	b40000a1 	cbz	x1, 4006a4 <register_tm_clones+0x34>
  400694:	90000002 	adrp	x2, 400000 <_init-0x538>
  400698:	f9457c42 	ldr	x2, [x2, #2808]
  40069c:	b4000042 	cbz	x2, 4006a4 <register_tm_clones+0x34>
  4006a0:	d61f0040 	br	x2
  4006a4:	d65f03c0 	ret

00000000004006a8 <__do_global_dtors_aux>:
  4006a8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006ac:	910003fd 	mov	x29, sp
  4006b0:	f9000bf3 	str	x19, [sp, #16]
  4006b4:	b0000093 	adrp	x19, 411000 <malloc@GLIBC_2.17>
  4006b8:	39412260 	ldrb	w0, [x19, #72]
  4006bc:	35000080 	cbnz	w0, 4006cc <__do_global_dtors_aux+0x24>
  4006c0:	97ffffe0 	bl	400640 <deregister_tm_clones>
  4006c4:	52800020 	mov	w0, #0x1                   	// #1
  4006c8:	39012260 	strb	w0, [x19, #72]
  4006cc:	f9400bf3 	ldr	x19, [sp, #16]
  4006d0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006d4:	d65f03c0 	ret

00000000004006d8 <frame_dummy>:
  4006d8:	17ffffe6 	b	400670 <register_tm_clones>

00000000004006dc <init>:
  4006dc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4006e0:	910003fd 	mov	x29, sp
  4006e4:	f9000bf3 	str	x19, [sp, #16]
  4006e8:	f90017a0 	str	x0, [x29, #40]
  4006ec:	d2800100 	mov	x0, #0x8                   	// #8
  4006f0:	97ffffa0 	bl	400570 <malloc@plt>
  4006f4:	aa0003e1 	mov	x1, x0
  4006f8:	f94017a0 	ldr	x0, [x29, #40]
  4006fc:	f9000001 	str	x1, [x0]
  400700:	f94017a0 	ldr	x0, [x29, #40]
  400704:	f9400013 	ldr	x19, [x0]
  400708:	d2800200 	mov	x0, #0x10                  	// #16
  40070c:	97ffff99 	bl	400570 <malloc@plt>
  400710:	f9000260 	str	x0, [x19]
  400714:	f94017a0 	ldr	x0, [x29, #40]
  400718:	f9400000 	ldr	x0, [x0]
  40071c:	f9400000 	ldr	x0, [x0]
  400720:	b900001f 	str	wzr, [x0]
  400724:	f94017a0 	ldr	x0, [x29, #40]
  400728:	f9400000 	ldr	x0, [x0]
  40072c:	f9400000 	ldr	x0, [x0]
  400730:	f900041f 	str	xzr, [x0, #8]
  400734:	d503201f 	nop
  400738:	f9400bf3 	ldr	x19, [sp, #16]
  40073c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400740:	d65f03c0 	ret

0000000000400744 <pop>:
  400744:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400748:	910003fd 	mov	x29, sp
  40074c:	f9000fa0 	str	x0, [x29, #24]
  400750:	f9400fa0 	ldr	x0, [x29, #24]
  400754:	f9400001 	ldr	x1, [x0]
  400758:	90000000 	adrp	x0, 400000 <_init-0x538>
  40075c:	912c0000 	add	x0, x0, #0xb00
  400760:	aa0103e2 	mov	x2, x1
  400764:	f9400fa1 	ldr	x1, [x29, #24]
  400768:	97ffff9a 	bl	4005d0 <printf@plt>
  40076c:	f9400fa0 	ldr	x0, [x29, #24]
  400770:	f9400000 	ldr	x0, [x0]
  400774:	f9400400 	ldr	x0, [x0, #8]
  400778:	f100001f 	cmp	x0, #0x0
  40077c:	540000a1 	b.ne	400790 <pop+0x4c>  // b.any
  400780:	90000000 	adrp	x0, 400000 <_init-0x538>
  400784:	912c6000 	add	x0, x0, #0xb18
  400788:	97ffff8a 	bl	4005b0 <puts@plt>
  40078c:	14000026 	b	400824 <pop+0xe0>
  400790:	f9400fa0 	ldr	x0, [x29, #24]
  400794:	f9400000 	ldr	x0, [x0]
  400798:	f9400400 	ldr	x0, [x0, #8]
  40079c:	b9400000 	ldr	w0, [x0]
  4007a0:	b9002fa0 	str	w0, [x29, #44]
  4007a4:	90000000 	adrp	x0, 400000 <_init-0x538>
  4007a8:	912cc000 	add	x0, x0, #0xb30
  4007ac:	b9402fa1 	ldr	w1, [x29, #44]
  4007b0:	97ffff88 	bl	4005d0 <printf@plt>
  4007b4:	f9400fa0 	ldr	x0, [x29, #24]
  4007b8:	f9400000 	ldr	x0, [x0]
  4007bc:	f9400400 	ldr	x0, [x0, #8]
  4007c0:	f90013a0 	str	x0, [x29, #32]
  4007c4:	f9400fa0 	ldr	x0, [x29, #24]
  4007c8:	f9400000 	ldr	x0, [x0]
  4007cc:	f9400401 	ldr	x1, [x0, #8]
  4007d0:	90000000 	adrp	x0, 400000 <_init-0x538>
  4007d4:	912ce000 	add	x0, x0, #0xb38
  4007d8:	aa0103e2 	mov	x2, x1
  4007dc:	f94013a1 	ldr	x1, [x29, #32]
  4007e0:	97ffff7c 	bl	4005d0 <printf@plt>
  4007e4:	f9400fa0 	ldr	x0, [x29, #24]
  4007e8:	f9400000 	ldr	x0, [x0]
  4007ec:	f9400401 	ldr	x1, [x0, #8]
  4007f0:	f9400fa0 	ldr	x0, [x29, #24]
  4007f4:	f9000001 	str	x1, [x0]
  4007f8:	f9400fa0 	ldr	x0, [x29, #24]
  4007fc:	f9400001 	ldr	x1, [x0]
  400800:	f9400fa0 	ldr	x0, [x29, #24]
  400804:	f9400000 	ldr	x0, [x0]
  400808:	f9400402 	ldr	x2, [x0, #8]
  40080c:	90000000 	adrp	x0, 400000 <_init-0x538>
  400810:	912d6000 	add	x0, x0, #0xb58
  400814:	97ffff6f 	bl	4005d0 <printf@plt>
  400818:	f94013a0 	ldr	x0, [x29, #32]
  40081c:	97ffff69 	bl	4005c0 <free@plt>
  400820:	b9402fa0 	ldr	w0, [x29, #44]
  400824:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400828:	d65f03c0 	ret

000000000040082c <push>:
  40082c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400830:	910003fd 	mov	x29, sp
  400834:	f9000fa0 	str	x0, [x29, #24]
  400838:	b90017a1 	str	w1, [x29, #20]
  40083c:	f9400fa0 	ldr	x0, [x29, #24]
  400840:	f9400001 	ldr	x1, [x0]
  400844:	90000000 	adrp	x0, 400000 <_init-0x538>
  400848:	912c0000 	add	x0, x0, #0xb00
  40084c:	aa0103e2 	mov	x2, x1
  400850:	f9400fa1 	ldr	x1, [x29, #24]
  400854:	97ffff5f 	bl	4005d0 <printf@plt>
  400858:	d2800200 	mov	x0, #0x10                  	// #16
  40085c:	97ffff45 	bl	400570 <malloc@plt>
  400860:	f90017a0 	str	x0, [x29, #40]
  400864:	f94017a0 	ldr	x0, [x29, #40]
  400868:	b94017a1 	ldr	w1, [x29, #20]
  40086c:	b9000001 	str	w1, [x0]
  400870:	f94017a0 	ldr	x0, [x29, #40]
  400874:	f9400401 	ldr	x1, [x0, #8]
  400878:	90000000 	adrp	x0, 400000 <_init-0x538>
  40087c:	912de000 	add	x0, x0, #0xb78
  400880:	aa0103e2 	mov	x2, x1
  400884:	f94017a1 	ldr	x1, [x29, #40]
  400888:	97ffff52 	bl	4005d0 <printf@plt>
  40088c:	f9400fa0 	ldr	x0, [x29, #24]
  400890:	f9400000 	ldr	x0, [x0]
  400894:	f9400401 	ldr	x1, [x0, #8]
  400898:	f94017a0 	ldr	x0, [x29, #40]
  40089c:	f9000401 	str	x1, [x0, #8]
  4008a0:	f94017a0 	ldr	x0, [x29, #40]
  4008a4:	f9400401 	ldr	x1, [x0, #8]
  4008a8:	f9400fa0 	ldr	x0, [x29, #24]
  4008ac:	f9400000 	ldr	x0, [x0]
  4008b0:	f9400402 	ldr	x2, [x0, #8]
  4008b4:	90000000 	adrp	x0, 400000 <_init-0x538>
  4008b8:	912e4000 	add	x0, x0, #0xb90
  4008bc:	97ffff45 	bl	4005d0 <printf@plt>
  4008c0:	f9400fa0 	ldr	x0, [x29, #24]
  4008c4:	f9400000 	ldr	x0, [x0]
  4008c8:	f94017a1 	ldr	x1, [x29, #40]
  4008cc:	f9000401 	str	x1, [x0, #8]
  4008d0:	f9400fa0 	ldr	x0, [x29, #24]
  4008d4:	f9400001 	ldr	x1, [x0]
  4008d8:	f9400fa0 	ldr	x0, [x29, #24]
  4008dc:	f9400000 	ldr	x0, [x0]
  4008e0:	f9400402 	ldr	x2, [x0, #8]
  4008e4:	90000000 	adrp	x0, 400000 <_init-0x538>
  4008e8:	912ec000 	add	x0, x0, #0xbb0
  4008ec:	f94017a3 	ldr	x3, [x29, #40]
  4008f0:	97ffff38 	bl	4005d0 <printf@plt>
  4008f4:	d503201f 	nop
  4008f8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4008fc:	d65f03c0 	ret

0000000000400900 <gettop>:
  400900:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400904:	910003fd 	mov	x29, sp
  400908:	f9000fa0 	str	x0, [x29, #24]
  40090c:	f9400fa0 	ldr	x0, [x29, #24]
  400910:	f100001f 	cmp	x0, #0x0
  400914:	54000081 	b.ne	400924 <gettop+0x24>  // b.any
  400918:	90000000 	adrp	x0, 400000 <_init-0x538>
  40091c:	912c6000 	add	x0, x0, #0xb18
  400920:	97ffff24 	bl	4005b0 <puts@plt>
  400924:	f9400fa0 	ldr	x0, [x29, #24]
  400928:	f9400000 	ldr	x0, [x0]
  40092c:	f9400400 	ldr	x0, [x0, #8]
  400930:	b9400000 	ldr	w0, [x0]
  400934:	b9002fa0 	str	w0, [x29, #44]
  400938:	b9402fa0 	ldr	w0, [x29, #44]
  40093c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400940:	d65f03c0 	ret

0000000000400944 <display>:
  400944:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400948:	910003fd 	mov	x29, sp
  40094c:	f9000fa0 	str	x0, [x29, #24]
  400950:	f9400fa0 	ldr	x0, [x29, #24]
  400954:	f9400000 	ldr	x0, [x0]
  400958:	f9400400 	ldr	x0, [x0, #8]
  40095c:	f90017a0 	str	x0, [x29, #40]
  400960:	f9400fa0 	ldr	x0, [x29, #24]
  400964:	f9400000 	ldr	x0, [x0]
  400968:	f100001f 	cmp	x0, #0x0
  40096c:	540000a1 	b.ne	400980 <display+0x3c>  // b.any
  400970:	90000000 	adrp	x0, 400000 <_init-0x538>
  400974:	912f6000 	add	x0, x0, #0xbd8
  400978:	97ffff0e 	bl	4005b0 <puts@plt>
  40097c:	14000010 	b	4009bc <display+0x78>
  400980:	90000000 	adrp	x0, 400000 <_init-0x538>
  400984:	912fc000 	add	x0, x0, #0xbf0
  400988:	97ffff12 	bl	4005d0 <printf@plt>
  40098c:	14000009 	b	4009b0 <display+0x6c>
  400990:	f94017a0 	ldr	x0, [x29, #40]
  400994:	b9400001 	ldr	w1, [x0]
  400998:	90000000 	adrp	x0, 400000 <_init-0x538>
  40099c:	91300000 	add	x0, x0, #0xc00
  4009a0:	97ffff0c 	bl	4005d0 <printf@plt>
  4009a4:	f94017a0 	ldr	x0, [x29, #40]
  4009a8:	f9400400 	ldr	x0, [x0, #8]
  4009ac:	f90017a0 	str	x0, [x29, #40]
  4009b0:	f94017a0 	ldr	x0, [x29, #40]
  4009b4:	f100001f 	cmp	x0, #0x0
  4009b8:	54fffec1 	b.ne	400990 <display+0x4c>  // b.any
  4009bc:	d503201f 	nop
  4009c0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4009c4:	d65f03c0 	ret

00000000004009c8 <main>:
  4009c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4009cc:	910003fd 	mov	x29, sp
  4009d0:	90000000 	adrp	x0, 400000 <_init-0x538>
  4009d4:	91302000 	add	x0, x0, #0xc08
  4009d8:	97fffef6 	bl	4005b0 <puts@plt>
  4009dc:	910063a0 	add	x0, x29, #0x18
  4009e0:	97ffff3f 	bl	4006dc <init>
  4009e4:	f9400fa0 	ldr	x0, [x29, #24]
  4009e8:	52800021 	mov	w1, #0x1                   	// #1
  4009ec:	97ffff90 	bl	40082c <push>
  4009f0:	f9400fa0 	ldr	x0, [x29, #24]
  4009f4:	52800041 	mov	w1, #0x2                   	// #2
  4009f8:	97ffff8d 	bl	40082c <push>
  4009fc:	f9400fa0 	ldr	x0, [x29, #24]
  400a00:	52800061 	mov	w1, #0x3                   	// #3
  400a04:	97ffff8a 	bl	40082c <push>
  400a08:	f9400fa0 	ldr	x0, [x29, #24]
  400a0c:	97ffffce 	bl	400944 <display>
  400a10:	f9400fa0 	ldr	x0, [x29, #24]
  400a14:	97ffff4c 	bl	400744 <pop>
  400a18:	f9400fa0 	ldr	x0, [x29, #24]
  400a1c:	97ffffca 	bl	400944 <display>
  400a20:	f9400fa0 	ldr	x0, [x29, #24]
  400a24:	97ffff48 	bl	400744 <pop>
  400a28:	f9400fa0 	ldr	x0, [x29, #24]
  400a2c:	97ffffc6 	bl	400944 <display>
  400a30:	f9400fa0 	ldr	x0, [x29, #24]
  400a34:	97ffff44 	bl	400744 <pop>
  400a38:	f9400fa0 	ldr	x0, [x29, #24]
  400a3c:	97ffffc2 	bl	400944 <display>
  400a40:	52800000 	mov	w0, #0x0                   	// #0
  400a44:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400a48:	d65f03c0 	ret
  400a4c:	00000000 	.inst	0x00000000 ; undefined

0000000000400a50 <__libc_csu_init>:
  400a50:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400a54:	910003fd 	mov	x29, sp
  400a58:	a901d7f4 	stp	x20, x21, [sp, #24]
  400a5c:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf3e0>
  400a60:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf3e0>
  400a64:	91374294 	add	x20, x20, #0xdd0
  400a68:	913722b5 	add	x21, x21, #0xdc8
  400a6c:	a902dff6 	stp	x22, x23, [sp, #40]
  400a70:	cb150294 	sub	x20, x20, x21
  400a74:	f9001ff8 	str	x24, [sp, #56]
  400a78:	2a0003f6 	mov	w22, w0
  400a7c:	aa0103f7 	mov	x23, x1
  400a80:	9343fe94 	asr	x20, x20, #3
  400a84:	aa0203f8 	mov	x24, x2
  400a88:	97fffeac 	bl	400538 <_init>
  400a8c:	b4000194 	cbz	x20, 400abc <__libc_csu_init+0x6c>
  400a90:	f9000bb3 	str	x19, [x29, #16]
  400a94:	d2800013 	mov	x19, #0x0                   	// #0
  400a98:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400a9c:	aa1803e2 	mov	x2, x24
  400aa0:	aa1703e1 	mov	x1, x23
  400aa4:	2a1603e0 	mov	w0, w22
  400aa8:	91000673 	add	x19, x19, #0x1
  400aac:	d63f0060 	blr	x3
  400ab0:	eb13029f 	cmp	x20, x19
  400ab4:	54ffff21 	b.ne	400a98 <__libc_csu_init+0x48>  // b.any
  400ab8:	f9400bb3 	ldr	x19, [x29, #16]
  400abc:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400ac0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400ac4:	f9401ff8 	ldr	x24, [sp, #56]
  400ac8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400acc:	d65f03c0 	ret

0000000000400ad0 <__libc_csu_fini>:
  400ad0:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400ad4 <_fini>:
  400ad4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400ad8:	910003fd 	mov	x29, sp
  400adc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400ae0:	d65f03c0 	ret
